The present invention relates to a semiconductor memory tester and, more particularly, to a memory tester additionally provided with a feature suitable for testing large capacity memories.
A dynamic random access memory (DRAM) employs a differential sense amplifier as a bit sense circuit for readout of memory cells. For example, as shown in FIG. 1, vertical lines A1, X2, ..., called word lines, are provided corresponding to X addresses (column addresses) and paired horizontal lines (Y1a, Y1b), (Y2a, Y2b), . . ., called bit lines, are provided corresponding to Y addresses (row addresses). The paired bit lines (Y1a, Y1b), (Y2a, Y2b), ... are each connected to alternate memory cells MC of a sequence of X addresses on the same Y address, and the paired bit lines are each connected at one end to non-inverting and inverting inputs of the corresponding one of sense amplifiers SA1, SA2, . . . With such an arrangement, even if a logical value "1" is written into a desired one of the memory cells, the output logic read out therefrom differs, depending on which of the two inputs of the sense amplifier the bit line connected to the desired memory cell MC is connected to. In view of this, the DRAM is adapted so that data stored in the memory cells MC may always be read out in correct logic, by storing the data intact or after inverting its logic, depending on which of the bit lines of each pair the memory cells MC are connected to. Such a function of the DRAM will hereinafter be referred to as an inversion feature. While the above prior art example has been described to employ a structure in which each Y address is accessed via a pair of bit lines, the prior art may sometimes use a structure of accessing each X address via a pair of bit lines and reading it out by a differential sense amplifier, or a combination of such two structures.
As the capacity of the DRAM increases to 4 M bits, 16 M bits, and so on, the coupling capacitance between the bit lines increases and the capacity of each memory cell decreases, reducing the SN ratio of readout. As a solution to this problem, the prior art employs a twisted bit-line system in which bit lines of each pair connected to a differential amplifier alternately cross each other to decrease coupling noise by the neighboring bit lines to thereby improve the SN ratio. Yet, this method involves complicated write control, because addresses to be written after inversion of the logic of data and to be written intact are mixed complicatedly.
A test of a memory equipped with such an inversion feature calls for a traditional test in which a test pattern signal composed of an address and data (composed of test data and expected data) is applied to the memory under test to write therein the test data at a specified address and the data is read out therefrom and checked for coincidence with the expected data, and a test which is made under the condition that data is written in the memory so that a storage area for holding polarity- or logic-inverted data and a storage area for holding non-inverted data may have the same polarity distribution, or the condition that "1's" or "0's" are written in the two storage areas throughout them.
Such a test could be made by modifying or revising a pattern generating program of the pattern generator which generates the test pattern, but the modification of the program is troublesome. Besides, since memories under test are not uniform in specifications and since the polarity-inverted data storage area and the non-inverted data storage area are not fixed, it is also cumbersome to revise the program to meet the specifications.
To avoid this, there has heretofore been proposed a tester which recognizes the polarity-inverted data storage area of the memory under test and permits freely selecting whether or not to "invert" the polarity of the test data signal when accessing the inverted data storage area.
FIG. 2 shows an example of such a conventional tester. Reference numeral 10 indicates a pattern generator, which includes an address generator 11 and a data generator 12 for creating test data and expected value data. An address signal AD available from the address generator 11 is applied to an address input terminal of a memory under test 20 to access it, and at the same time, test data signal TD is applied from the data generator 12 to the memory 20 at the accessed address to effect a write therein or readout therefrom.
A response output OD read out of the memory under test 20 is provided to a logic comparator 30, which compares the output OD with expected value data ED from the data generator 12 and outputs the result of comparison CR. Where the result of comparison CR indicates a mismatch, it is decided that the memory under test 20 is faulty. In some cases, the result of comparison CR is stored in a fail memory (not shown) for a failure analysis of memories.
Polarity switches 15 and 16 are provided in a path 13 of the test data signal TD from the data generator 12 to the memory under test 20 and a path of the expected value data ED from the data generator 12 to the logic comparator 30. The polarity switches 15 and 16 are controlled by a polarity control signal CS available from a polarity controller 40 so that the polarity of the test data signal TD to be written into the memory under test 20 can be selected for each storage area being addressed.
The polarity controller 40 is made up of inverted area memories 41, 42 and 43 provided for recognizing a polarity-inverted data storage area of the memory under test 20, an inversion data register 44 for determining whether or not to invert the polarity of the test data signal TD which is applied to the polarity-inverted data storage area and the expected value data ED, and an inversion data selector 45 which selectively outputs inversion data stored in the inversion data register 44.
In this example, X, Y and Z address signals AX, AY and AZ are employed, which are applied to the three inverted area memories 41, 42 and 43, respectively, to access them individually.
For example, a "1" logic is prestored in the inverted area memories 41, 42 and 43 at addresses corresponding to the polarity-inverted data storage areas of the memory under test 20. Now, let it be assumed, for the sake of brevity, that the memory under test 20 has a capacity of 256 bits, that its memory cells are each accessed using a 4-bit X address AX=X.sub.0 X.sub.1 X.sub.2 X.sub.3, a 4-bit Y address AY=Y.sub.0 Y.sub.1 Y.sub.2 Y.sub.3 and that no Z address is used. Consider that the entire area of the memory 20 is divided into a hatched polarity-inverted data storage area INV and a blank non-polarity inverted data storage area NINV as shown in FIG. 3. In this instance, as will be seen from FIG. 3, the X address AX in the polarity-inverted data storage area is expressed by AX=**11, where * is a "0" or "1", and the Y address AY is expressed by AY=**11. Hence, in the X address inverted area memory 41 there are prestored "1's" at addresses "0011" to "1111" as depicted in FIG. 4A, whereas in the Y address inverted area memory 42 there are prestored "1's" at addresses "0011" to "1111" as depicted in FIG. 4B. Consequently, when an address in the polarity-inverted data storage area of the memory under test 20 is read out of the address generator 11, the "1" logic is read out of each of the inverted area memories 41, 42 and 43.
Pieces of data x, y and z read out of the inverted area memories 41, 42 and 43 are input, as a 3-bit select signal, into the inversion data selector 45. The inversion data selector 45 responds to the 3-bit select signal xyz to select and output inversion data prestored in the inversion data register 44 for determining whether or not to invert the test data signal.
The inversion data register 44 can be formed by, for example, an 8-bit register. When the select signal xyz composed of the data read out of the three inverted area memories 41, 42 and 43 is any one of "000" to "111", the inversion data selector 45 outputs corresponding one of first to eighth bits B.sub.1 to B.sub.8 of the inversion data register 44 as shown in FIG. 5. In the case where the memory under test 20 has the polarity-inverted data storage area INV as depicted in FIG. 3, if at least one of the pieces of data or bits x and y read out by the X and Y addresses AX and AY from the X and Y address inverted area memories 41 and 42 shown in FIG. 4A and 4B is a "1", then the memory cell specified by the X and Y addresses AX and AY is within the polarity-inverted data storage area INV; therefore, "1's" are prestored at all of those bit positions in the inversion data register 44 which are selected by the select signal xyz in which at least one of its bits x and y goes to a "1". Thus, there are stored, for example, "0, 1, 1, 1, 0, 1, 1, 1" in the 8-bit register 44 as shown in FIG. 5. That is, when the select signal xyz is either "000" or "001", inversion data "0" of either the first or fifth bits B.sub.1 or B.sub.5 is selected and provided to the polarity switches 15 and 16. When the select signal xyz is any one cf "100", "010", "110", "101", "011" and "111", the inversion data selector 45 selects inversion data "1" at a corresponding one of the second, third, fourth, sixth, seventh and eighth bits B.sub.2, B.sub.3, B.sub.4, B.sub.6, B.sub.7 and B.sub.8, and provides the inversion data of the logic "1" to the polarity switches 15 and 16.
The polarity switches 15 and 16 in this example are shown to be formed by exclusive-OR circuits. When they are supplied with the inversion data of the logic "0" from the inversion data selector 45, the test data signal TD and the expected value data ED from the data generator 12 are applied intact to the memory under test 20 and the logic comparator 30 without being inverted in polarity (i.e. logic). On the other hand, when supplied with the inversion data of the logic "1", the polarity switches 15 and 16 invert the polarities of the test data signal TD and the expected value data ED from the data generator 12 which are applied to the memory under test 20 and the logic comparator 30. Consequently, in the above example the test data signal TD to be written into the polarity-inverted data storage area INV in FIG. 3 is inverted in logic. As will be appreciated from the above, the polarity-inverted data storage area INV of the memory under test 20 can be altered by modifying data to be prestored in the X and Y address inverted region memories 41 and 42 shown in FIGS. 4A and 4B and/or data to be prestored in the inversion data register 44 shown in FIG. 5. In the FIG. 3 example of the polarity-inverted data storage area INV, the polarity inversion takes place in areas where high-order two bits X.sub.2 and X.sub.3 of the X address AX=X.sub.0 X.sub.1 X.sub.2 X.sub.3 are both "1's" and areas where high-order two bits Y.sub.2 and Y.sub.3 of the Y address AY =Y.sub.0 Y.sub.1 Y.sub.2 Y.sub.3 are both "l'"; hence, the polarity-inverted data storage area INV is specified by addresses AX, AY, AZ which satisfy the following logical expression: EQU 1=X.sub.2 .multidot.X.sub.3 +Y.sub.2 .multidot.Y.sub.3 ( 1)
In the conventional semiconductor memory tester shown in FIG. 2, however, as represented by the example of the logical expression (1), the polarity-inverted data storage areas that can be specified are limited to only simple ones, because the basic principle of specifying the polarity-inverted data storage area is based on the specifying of the X address polarity inverted area, the Y address polarity inverted area and the Z address polarity inverted area by the A address AX, the Y address AY and Z address AX (X.sub.2 .multidot.X.sub.3 and Y.sub.2 .multidot.Y.sub.3 in the logical expression (1), for example) and on the selection of a combination of the specified areas (a logical sum or logical product, for instance, the logical sum of X.sub.2 .multidot.X.sub.3 and Y.sub.2 .multidot.Y.sub.3 in the above-mentioned logical expression). For example, the hatched polarity-inverted data storage area in FIG. 6 can be specified by addresses which satisfy the following logical expression (2) in which X.sub.3 and Y.sub.2 in the logical expression (1) are exchanged with each other: EQU 1=X.sub.2 .multidot.Y.sub.2 +X.sub.3 .multidot.Y.sub.3 ( 2)
With the device shown in FIG. 2, however, it is impossible to specify such a polarity-inverted data storage area as expressed by the logical expression (2). That is to say, a polarity-inverted data storage area, which is expressed by a logical expression including at least two of the logical AND between the X and Y addresses AX and AY, the logical AND between the X and Z addresses AX and AZ and the logical AND between the Y and Z addresses AY and AZ, cannot be specified except in special cases.
The prior art device calls for large-capacity memories as the inverted area memories 41, 42 and 43, because they need to have a bit capacity corresponding to the number of all addresses used which is determined by the address length of the X, Y and Z address signals AX, AY and AZ. For example, when the address signals AX, AY and AZ are 16-bit, 64 K-bit memories are needed for the X, Y and Z inverted area memories 41, 42 and 43. No Z address may sometimes be needed and when used, it may be appreciably shorter than the X and Y addresses in many cases.